The present invention relates generally to semiconductor manufacturing processes, and more particularly to oxide isolation processing techniques used in the fabrication of submicron geometry integrated circuit devices.
In the past two decades Very Large Scale Integration ("VLSI") process technologies have evolved from generation to generation with ever increasing chip packing densities and shrinking layout design rules. Fundamental to Integrated Circuit ("IC") device manufacturing is the fabrication of extremely large numbers of isolated active areas on the surface of a thumb-nail size chip of silicon, each active area typically being the site of one or more transistor elements. A single chip can contain in excess of one million transistors and many thousands of active areas. Of course, many such chips are fabricated side-by-side simultaneously as distinct but integral parts of a large silicon wafer. Present day fabrication facilities ("Fabs") are equipped to process eight-inch diameter wafers.
Prominent among the conventional process technologies in use today are various CMOS processes in which complementary P-channel and N-channel metal oxide semiconductor field effect transistors ("MOSFETs") are fabricated and interconnected on the same chip. State-of-the-art processes are now achieving feature sizes (e.g., gate widths) of slightly under 0.3 microns. The present invention is particularly applicable to such high performance CMOS processes, but may be useful as well in other conventional MOS processes.
A common feature of such MOS processes is the use of thick layers of silicon dioxide ("oxide") to isolate adjacent active areas on a silicon chip. In one common oxide isolation technique, thick ribbons of "field oxide" are grown in selected areas using standard masking techniques. Today's advanced process technologies rely upon a field oxide of a specified minimum thickness to block dopant penetration into the silicon underlying the field oxide during conventional ion implantation steps. Ion implantation is used to introduce dopants such as phosphorus and boron into the silicon to form transistor source and drain regions in the active areas. Penetration of the field oxide by such dopants would short out transistors in neighboring active areas, thus defeating the isolation function of the field oxide and effectively preventing the fabrication of operational IC devices.
Because a minimum thickness for the field oxide is required to prevent dopant penetration, the field oxide has become a limiting factor in achieving relatively high packing densities in submicron feature size processes. This problem is due in part to the inherent nature of oxide growth in which the oxide spreads laterally while growing on the silicon surface, producing a field oxide that is thicker in the middle than at the edges. The tapered portions on each side of the field oxide constitute "transition zones" that waste valuable silicon real estate.
One alternative has been to deposit the isolation oxide in an etched trench, which enables the fabrication of deep yet narrow oxide walls isolating adjacent active areas. However, this technique has its own particular set of fabrication and functionality problems.
Thus, it would be desirable to be able to employ a grown oxide as an isolation oxide with a relatively narrow width while maintaining sufficient oxide thickness in the field area to prevent dopant penetration during ion implantation.
In order to fully appreciate the improvement achieved by the present invention, the following description is provided with reference to FIGS. 1-5 showing the relevant steps in a prior art process using a grown field oxide.
Referring to FIG. 1, a small upper portion of an IC chip 10 is shown in cross section at an early stage in the fabrication process. The chip 10 includes a silicon substrate 12, which typically is lightly doped so that it can be readily counterdoped to enable the formation of transistor regions therein. For example, the substrate 12 may comprise 8 ohm-centimeter resistivity monocrystalline silicon. Alternatively, the substrate 12 may include a heavily doped lower portion (not shown) and a lightly doped epitaxial layer in its upper portion, which is illustrated in FIG. 1. In illustrating the substrate 12, cross-hatching has been left off for clarity.
In a CMOS process, wells of complementary conductivity are provided in the upper portion of the substrate. There are many such wells arranged to enable fabrication of very large numbers of P-channel and N-channel MOS transistors at discrete locations on the chip 10. In the example of a CMOS process, only the upper portion of one such well is shown in FIG. 1. Whether the well is N-type or P-type, the process steps as described below are substantially the same but with dopants of opposite conductivity types being used in corresponding regions of the opposite conductivity type wells. For simplicity, the description of FIGS. 1-5 will assume that the fabrication is occurring in a P-type well where an N-channel transistor is shown being formed. As used herein, "N-channel transistor" describes a MOSFET with N-type source and drain regions, and "P-channel transistor" describes a MOSFET with P-type source and drain regions.
A thin oxide layer 14 is provided on the chip 10, preferably by thermal oxidation of the top surface of the silicon substrate 12. For example, oxide layer 14 may be grown to a thickness of about 150 .ANG.. Atop the oxide layer 14 are layers 16 and 17 of silicon nitride, which are derived from a single deposited nitride layer using a conventional photolithographic technique. Nitride layers 16 and 17 are two of many such layers used to define active areas in the upper portion of the substrate 12.
Present day photolithography employs a series of masking and chemical processing steps to form patterned layers in precise locations on the surface of a semiconductor substrate. The following is a general description of such commonly employed photolithography, which need not be illustrated because the techniques are well known. An image, which corresponds to one "die" or "chip" on a wafer containing many such individual chips, is contained in a "reticle," which is a type of optical plate. An ultraviolet ("UV") light is passed through the reticle and is optically reduced in size by a factor, such as a 5 to 1 reduction. The light is focused on the wafer in registration with one chip location and exposes a thin UV sensitive layer of photoresist, which has been deposited on the wafer. The light chemically alters the exposed portion of the photoresist. Following a development process, the unexposed portions of the photoresist can be removed chemically leaving a high resolution photoresist mask on the surface of the wafer. The exposure process is repeated through a stepping operation for each chip location prior to the development and selective removal steps. As those skilled in the art know well, precise registration of each photoresist mask in a series of such masking operations is necessary for achieving operational devices. As process technology has advanced, mask misalignment tolerances have tightened commensurate with each decrease in feature sizes, which are now well into the submicron range.
Referring to FIG. 2, an illustrative example of a top surface pattern is shown. In the small area of the silicon chip shown, the nitride layer 16 assumes a square shape. Nitride layer 17, which is only partially shown, may also be square or may be some other shape as layout needs dictate. An active area 18 is shown in FIG. 2 as the dashed square confined within the outline of the larger square nitride layer 16. The actual edges of the active area 18 are defined by a field oxide formed in subsequent processing. Thus, the dashed square is included in FIG. 2 merely to illustrate where the active area 18 will lie following the subsequent field oxide formation, which will now be described.
In FIG. 3, the portion of the silicon chip 10 is shown after a series of processing steps following the stage shown in FIG. 1. The principal step in the sequence is a thermal oxidation step for an extended duration, which initially grows silicon dioxide on the surface of the silicon chip in the areas not covered by nitride layers 16 and 17 and other such nitride layers not shown in the figure. As the thermal oxidation proceeds, oxide grows laterally under the edges of the silicon nitride layers, bending them upward in the process. This occurs due to oxygen penetrating laterally and downward through the thin oxide layer 14 under the edges of the nitride layers to the underlying silicon surface where the oxidation reaction occurs. The thermal oxidation step is halted when the growing oxide layer reaches a desired thickness (e.g., 4000 .ANG.). Then, the nitride layers and the underlying thin oxide layer 14 are stripped away using conventional etching techniques to arrive at the structure depicted in FIG. 3.
After such conventional processing steps, a thick field oxide layer 20 is provided having the cross-sectional profile shown in FIG. 3. The field oxide 20 has tapered edge portions or transition zones T, which extend from a thick middle portion F to points defining the boundaries of the active areas. To provide a visual understanding of the top surface pattern, the transition zones T are shown as the shaded areas confined within the dashed outlines in FIG. 2. The pointed edges of the transition zones T define the boundaries of the active areas, such as the square active area 18. Typically, the width of each transition zone T approximately equals the maximum field oxide thickness, which in this case is about 4000 .ANG..
Now referring to FIG. 2a, a line chart is shown corresponding in location to the cross section line in FIG. 2. FIG. 2a shows the locations of the transition zones T, the full thickness field oxide portion F, and the active area 18, which is labeled .ANG.. FIG. 2a illustrates the fact that a relatively large portion of the silicon surface is allocated to the transition zones T.
Referring again to FIG. 3, a doped region 22 illustrated by stippling is present just below the field oxide 20. This doped region 22 is called a channel stop, and serves as the name implies to prevent unwanted inversion of the conductivity of the silicon just below the field oxide 20 during operation of the IC device. In the example of a P-type well, a gate interconnect layer (not shown) passing over the field oxide 20 could induce a conductive channel of electrons under the field oxide in much the same way as an N-channel MOSFET turns on. But for the channel stop, such an unwanted channelling effect under the field oxide might occur in the event that such an overlying gate interconnect layer carries a voltage transient above nominal gate levels. To prevent such unwanted channelling, the P-type doping is increased immediately under the field oxide 20. Typically, this is accomplished prior to growth of the field oxide by a boron ion implant step to introduce a relatively heavy dose of boron atoms into the portions of the silicon surface not covered by the nitride layers. See FIG. 1. Preferably, boron difluoride (BF.sub.2) molecules are implanted through the thin oxide layer 14 while the relatively thick nitride layers 16, 17 are used to block the molecules penetration through to the underlying silicon.
Now referring to FIG. 4, the portion of the chip 10 undergoing processing is shown at a subsequent stage in the fabrication process. Steps leading to this stage include growth of a thin gate oxide layer 24, formation of a conductive polycrystalline silicon ("polysilicon") gate layer 26, and the deposition of a silicon dioxide layer 28 of about 1500 .ANG. to 2000 .ANG. in thickness over the entire surface of the chip 10. The thickness of the gate oxide layer 24 in present day high performance CMOS processes is under 100 .ANG. and is typically about 70 .ANG. for the most advanced processes. For conceptual clarity of illustration, the figures exaggerate the relative thickness of gate oxide layer 24. The polysilicon gate 26 is typically about 3000 .ANG. thick (i.e., tall) and 3000 .ANG. wide for such advanced processes.
Prior to deposition of oxide layer 28, lightly doped transistor regions 30 and 32 are formed by an ion implantation step. In the P-type well, the transistor being fabricated will be an N-channel MOSFET, in which case a dose of phosphorus ions is implanted in self-aligned registration with the gate 26. A typical dose would be 2.times.10.sup.13 ions/cm.sup.2 at an implant energy of 30 KeV. The N-type regions 30 and 32 thus formed are shown driven to a slight depth into the upper surface of the substrate 12, but in reality such a drive step does not occur until a later stage in the process. Once driven, the lightly doped regions 30 and 32 will extend slightly under the edges of the gate 26 and define a channel therebetween. For a gate of 0.3 microns (i.e., 3000 .ANG.), the channel length would of course be slightly less than 0.3 microns due to the lateral diffusion of regions 30 and 32 slightly under the gate 26.
As a result of a number of conventional etching and cleaning steps performed between the stages of FIGS. 3 and 4, the shape and thickness of the field oxide 20 has changed. The maximum thickness in the center of the field oxide has been diminished from about 4000 .ANG. to less than 3000 .ANG. and perhaps as little as 2500 .ANG.. Also, the contour of the top surface of each of the transition zones T has changed from a generally convex shape to a concave shape sometimes referred to as a "bird's beak" characteristic.
Now referring to FIG. 5, the chip 10 is shown following partial removal of oxide layer 28 and an additional ion implantation step. Using a conventional anisotropic etching step, the oxide layer 28 of FIG. 4 is substantially removed except for oxide spacers 34 and 36 as shown in FIG. 5. As deposited, the oxide layer 28 conforms with a fairly uniform thickness to the surfaces of the underlying structure. Thus, when oxide layer 28 is removed by anisotropic etching, it comes off at a relatively constant vertical rate. Applying this phenomenon to advantage, the etch can be stopped when all portions of layer 28 except for the oxide spacers 34 and 36 have been removed. In practice, the anisotropic etch is stopped just after the oxide clears from atop the polysilicon layer 26 at a point when portions of the gate oxide 24 adjacent to the field oxide 20 have also been etched away to expose the underlying silicon surface of the substrate 12.
Then, for the N-channel transistor example shown, a relatively heavy phosphorus ion implantation step is performed to provide heavily doped regions 38 and 40. Preferably, a double implant is used in which phosphorus and arsenic atoms are implanted in successive steps, both being N-type dopants but with different atomic weights. A typical phosphorus dose would be 5.times.10.sup.14 ions/cm.sup.2 at an implant energy of 30 KeV, and a typical arsenic dose would be 5.times.10.sup.15 ions/cm.sup.2 at an implant energy of30 KeV. In the final device after a drive-in procedure has been performed, the phosphorus defines the PN junction depth at about 700 .ANG. below the surface, while the arsenic reaches a maximum depth of about 300 .ANG.. The very high arsenic doping concentration (at about the solubility limit in silicon) provides a very low resistivity in the N-type source and drain regions. The junction-defining phosphorus dopants achieve a relatively low leakage current by keeping the depletion layer (i.e., the layer that is depleted of charge on opposite sides of the PN junction during operation) from reaching the arsenic-doped region under normal operating voltage conditions.
The heavily doped regions 38 and 40 overlap the respective lightly doped regions 30 and 32, so that there is effectively only one source region (e.g., combined regions 30 and 38) and one drain region (e.g., combined regions 32 and 40) for each transistor. This technique has become standard in current practice in the fabrication of MOS integrated circuits and has become known as the lightly doped drain ("LDD") process. As those skilled in the art will appreciate, the LDD process is employed to provide MOSFETs having higher gains and other performance improvements relative to transistors having uniformly doped source and drain regions characteristic of processes used in years past. It will also be appreciated that in CMOS devices, P-channel LDD transistors are formed in the N-type wells using a similar sequence of steps in which light and heavy doses of boron are implanted to form the source and drain regions.
Although FIG. 5 shows a depth distinction between the lightly doped and heavily doped portions of the source and drain regions, they are depicted in this way merely to facilitate an understanding of the doping concentration differentiations. In actual practice the depths of the lightly doped and heavily doped portions may be indistinguishable, both extending to a depth from about 500 .ANG. to about 700 .ANG. below the silicon surface. Also, this final PN junction depth in not reached until after the aforemention drive-in procedure has been performed. The drive-in procedure preferably is performed as part of an oxide "reflow" procedure in which subsequently deposited oxide layers (not shown) are heated to a relatively high temperature, which substantially smoothes out the surface irregularities caused by the patterns of underlying conductive and insulating layers.
It will be appreciated that the above described process requires a final oxide thickness of at least about 2500 .ANG. in the middle portion of the field oxide 20 to block the heavy ion implantation dose used to create the heavily doped portions 38 and 40 of the source and drain regions shown in FIG. 5. Since the field oxide 20 is reduced in thickness as a consequence of standard etching and cleaning steps in the course of processing, it has been standard practice to start with about 4000 .ANG. of oxide as depicted in FIG. 3 to assure a minimum of 2500 .ANG. of oxide when the heavy ion implantation dose is applied at the stage of FIG. 5. Because the formation of a 4000 .ANG. thick field oxide layer 20 as shown in FIG. 3 produces relatively wide transition zones T by lateral oxide growth, this technique has been viewed as relatively inefficient in chip area utilization, particularly in state-of-the-art submicron processes.